1. Field
This disclosure relates generally to phase/frequency detectors, and more specifically, to a phase/frequency detector for a phase-locked loop (PLL) that samples on both rising and falling edges of a reference signal.
2. Related Art
In a PLL, a phase/frequency detector compares the phase of the reference signal to the phase of a divided voltage controlled oscillator (VCO) signal. The output of the phase detector then drives a charge pump which in turn drives a loop filter followed by a VCO. The VCO produces the VCO signal which is divided by a loop divider to generate the divided VCO signal.
FIG. 1 illustrates, in partial block diagram form and partial logic diagram form, a phase/frequency detector 10 in accordance with the prior art. Phase/frequency detector 10 includes D-type flip flops 12 and 14, a delay element 18, and NAND logic gate 16. The D inputs of flip flops 12 and 14 are tied to a high logic level. One flip flop is clocked by a reference signal FREF, the other flip-flop is clocked by a feedback signal FBACK that is provided by a voltage controlled oscillator (VCO) of a PLL. The Q outputs of flip-flops 12 and 14 are combined by NAND gate 16 and the result of the logic operation is delayed by delay element 18 before being used to reset the flip-flops. The Q output of each flip-flop is used to enable a charge pump. One charge pump provides a positive current to the VCO; the other charge pump provides negative current to the VCO. Charge is added to correct phase mismatch between the reference signal and the feedback signal.
This phase detector circuit is generally adequate for most applications. However, loop bandwidth of the PLL is limited by the reference frequency. Because the PLL is updated at the reference frequency, stability considerations require the loop bandwidth to be much smaller than the reference frequency. Higher PLL bandwidth is desirable because it leads to reduction of noise and static phase offset. This can be achieved if the reference frequency is increased. However, in many systems the reference frequency is fixed and cannot be increased, limiting achievable noise and static phase offset performance.
Therefore, what is needed is a PLL that circumvents the above limitations.